DESIGN OF HIGH SPEED DIGITAL COMMUNICATION SIGNAL PROCESSING SYSTEM BASED ON C LANGUAGE

In order to solve the problem of high bit error rate caused by frequent multiplication and accumulation operation of convolution module in digital communication, a high-speed digital communication signal processing system is designed based on C language. In the hardware part, with AD9364 chip as the core, the receiving channel and transmitting channel are designed to simulate and calibrate the digital signal to solve the DC bias and quadrature error. In the software part, the output signal of the loop filter is controlled, the channelized digital synchronous carrier model is constructed, and the convolution operation module is designed by using C language to improve the multiplication and accumulation operation ability. The symbol synchronization loop algorithm of communication signal is designed, the deviation between interpolation time and optimal sampling time is calculated, and the timing error is determined. The system test results show that under different SNR conditions, the measured and theoretical BER curves are basically consistent, and the difference between them is within 1dB at higher SNR, which is acceptable within the allowable error range, which verifies the effectiveness of the whole system scheme.