8X8 VEDIC MULTIPLIER USING REVERSIBLE LOGIC GATE

As multiplication needs more iterations, a longer processing time, and a larger system footprint than other computations, it is the multiplier that has the most impact on the performance of DSP applications. Hence, a high-speed, low-power multiplier is necessary to enhance the system's performance. The ancient discipline of mathematics known as Vedic Mathematics uses a special method of computation based on 16 Sutras. It employs the Urdhva Triyagbhyam Vedic technique, one of the 16 sutras. The Urdhva Triyagbhyam algorithm (sutra) of Vedic mathematics is used for multiplication to increase the speed, power, and area of multipliers. It is implemented using reversible logic gates. Reversible logic is extremely effective at reducing power loss. In this paper, literature survey for Vedic Multiplier is described. A detailed study on Various reversible logic gates used for Vedic Multiplication is presented here. 8 X 8 Vedic multiplication using Han-Carlson adder is shown here using an example.